A method for fabricating a semiconductor device using only four masks is disclosed in U.S. patent application Ser. No. 12/722,384 filed Mar. 11, 2010, entitled “SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT”, the entire contents of which are incorporated herein by reference. The method includes forming a plurality of trenches by applying a first mask, forming a first conductive region in the plurality of trenches, forming an intermediate dielectric region and a termination protection region by applying a second mask, forming a second conductive region in at least some of the trenches, forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region by applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region by applying a fourth mask.
This integrated structure involves power MOSFET devices that implement a body diode. However, typical P-N junction diodes exhibit undesirable characteristics during operation. These undesirable characteristics include: large forward conduction loss, storage of charge between body-epitaxial junction when operating in forward bias, excess stored minority charges which cause large recovery currents and voltage overshoots when the power MOSFET is switched from forward bias to reverse bias, and phase node voltage overshooting/ringing when implemented in a DC-DC converter application.
Schottky diodes, on the other hand, exhibit several desirable characteristics which make it preferable over P-N junction diodes, particularly in power MOSFET configurations. The low forward drop of the Schottky diode during forward conduction reduces power dissipation of the device and leads to lower conduction loss. The conduction of the Schottky is carried out by majority carriers, so minority carrier charge storage effects do not occur during switching of the device.
It is within this context that embodiments of the present invention arise.